Desktop Boards — Port 80h POST codes

Desktop Boards

Port 80h POST codes

This document defines the beep codes, error messages, and POST codes associated with BIOS versions based on Extensible Framework Interface (EFI).

Beep codes
BIOS error messages
Port 80h POST codes
Displaying POST codes
POST code ranges
POST codes
Typical POST sequence

Beep codes
The onboard speaker emits audible error codes (beep codes) during POST. Not all Intel® Desktop Boards include an onboard speaker.

Type	Pattern	Frequency
Memory error	Three long beeps	1,280 Hz
Thermal warning	Four alternating beeps: High tone, low tone, high tone, low tone	High tone: 2,000 Hz Low tone: 1,600 Hz

BIOS error messages

Error Message	Explanation
A processor that was not meant to be used with this board has been detected. Using an unsupported processor can result in improper operation, damage to the desktop board or processor or reduced product life. System shuts down in 10 seconds.	The installed processor is not compatible with the desktop board.
CMOS Battery Low	The battery could be losing power. Replace the battery soon.
CMOS Checksum Bad	The CMOS checksum is incorrect. CMOS memory can be corrupted. Run Setup to reset values.
Memory Size Decreased	Memory size has decreased since the last boot. If no memory was removed, the memory might be bad.
No Boot Device Available	System did not find a device to boot.

Port 80h POST codes
During the Power-On Self Test (POST), the BIOS sends progress codes (POST codes) to I/O port 80h. If the POST fails, the last POST code generated is left at port 80h. This code can be used to find out why the error occurred.

Displaying POST codes
You can display POST codes using either of the following methods.

POST card (PCI add-in card)	The POST card decodes the port and displays the contents on an LED display. The POST card must be installed in PCI bus connector 1.
Onboard POST code LED display	Some Intel® Desktop Boards include an onboard LED to show POST codes.

Port 80h POST code ranges
In the tables below, all POST codes and range values are listed in hexadecimal.

Range	Category/Subsystem
00 � 0F	Debug codes: Can be used by any PEIM/driver for debug.
10 � 1F	Host Processors
20 � 2F	Memory/Chipset
30 � 3F	Recovery
40 � 4F	Reserved for future use.
50 � 5F	I/O Busses: PCI, USB, ISA, ATA, etc.
60 � 6F	Reserved for future use (for new busses).
70 � 7F	Output Devices: All output consoles.
80 � 8F	Reserved for future use (new output console codes).
90 � 9F	Input devices: Keyboard/Mouse.
A0 � AF	Reserved for future use (new input console codes).
B0 � BF	Boot Devices: Includes fixed media and removable media.
C0 � CF	Reserved for future use.
D0 � DF	Boot device selection.
E0 � FF	E0 - EE: Miscellaneous codes F0 � FF: FF processor exception

Port 80h POST codes

POST Code	Description of POST Operation
00 - 0F	Debug Codes: can be used by any PEIM/driver for debug
10 - 1F	Host Processor
10	Power-on initialization of the host processor (Boot Strap Processor)
11	Host processor Cache initialization (including APs)
12	Starting Application processor initialization
13	SMM initialization
14	LAN initialization
15	Exit early platform init driver
16	SMBUS driver initialization
17	Entry to SMBUS execute read/write
19	Entry to CK505 programming
1F	Unrecoverable CPU error
20 - 2F	Memory / Chipset
21	Initializing a chipset component
22	Reading SPD from memory DIMMs
23	Detecting presence of memory DIMMs
24	Programming timing parameters in the memory controller and the DIMMs
25	Configuring memory
26	Optimizing memory settings
27	Initializing memory, such as ECC init
28	Testing memory
2F	No memory detected or no useful memory detected
30 - 3F	Recovery
30	Crisis Recovery has initiated per User request
31	Crisis Recovery has initiated by software (corrupt flash)
34	Loading recovery capsule
35	Handing off control to the recovery capsule
3F	Unable to recover
50 - 5F	I/O Busses (PCI, USB, ISA, ATA, etc.)
50	Enumerating PCI busses
51	Allocating resources to PCI bus
52	Hot Plug PCI controller initialization
53 � 57	Reserved for PCI Bus
58	Resetting USB bus
59	Reserved for USB
5A	Resetting PATA/SATA bus and all devices
5B	Reserved for ATA
5C	Resetting SMBUS
5D	Reserved for SMBUS
5F	Unrecoverable I/O bus error
70 - 7F	Output Devices
70	Resetting the VGA controller
71	Disabling the VGA controller
72	Enabling the VGA controller
78	Resetting the console controller
79	Disabling the console controller
7A	Enabling the console controller
7F	Unrecoverable output device error
90 - 9F	Input Devices
90	Resetting keyboard
91	Disabling keyboard
92	Detecting presence of keyboard
93	Enabling the keyboard
94	Clearing keyboard input buffer
95	Instructing keyboard controller to run Self Test (PS2 only)
98	Resetting mouse
99	Disabling mouse
9A	Detecting presence of mouse
9B	Enabling mouse
9F	Unrecoverable input device (keyboard or mouse) error
B0 - BF	Boot Devices
B0	Resetting fixed media
B1	Disabling fixed media
B2	Detecting presence of a fixed media (IDE hard drive detection etc.)
B3	Enabling/configuring a fixed media
B8	Resetting removable media
B9	Disabling removable media
BA	Detecting presence of a removable media (IDE, CD-ROM detection, etc.)
BC	Enabling/configuring a removable media
BF	Unrecoverable boot device error
D0 - DF	Boot Device Selection
Dy	Trying boot selection y (y=0 to 15)
E0 - FF	Miscellaneous Codes
E0	Started dispatching PEIMs (emitted on first report of EFI_SW_PC_INIT_BEGIN EFI_SW_PEI_PC_HANDOFF_TO_NEXT)
E2	Permanent memory found
E1, E3	Reserved for PEI/PEIMs
E4	Entered DXE phase
E5	Started dispatching drivers
E6	Started connecting drivers
E7	Waiting for user input
E8	Checking password
E9	Entering BIOS setup
EB	Calling Legacy Option ROMs
EF	Boot/S3 resume failure
F4	Entering Sleep state
F5	Exiting Sleep state
F8	EFI boot service ExitBootServices ( ) has been called
F9	EFI runtime service SetVirtualAddressMap ( ) has been called
FA	EFI runtime service ResetSystem ( ) has been called
FF	Processor exception

Typical Port 80h POST sequence
Port 80h code values typically increase during the boot process. The early codes are for subsystems closer to the processor and the later codes are for peripherals. Generally, the order of initialization is Processor -> Memory -> Busses -> Output/Input Devices -> Boot Devices. The sequence of POST is system-specific.

POST Code	Description
21	Initializing a chipset component
22	Reading SPD from memory DIMMs
23	Detecting presence of memory DIMMs
25	Configuring memory
28	Testing memory
34	Loading recovery capsule
E4	Entered DXE phase
12	Starting Application processor initialization
13	SMM initialization
50	Enumerating PCI busses
51	Allocating resourced to PCI bus
92	Detecting the presence of the keyboard
90	Resetting keyboard
94	Clearing keyboard input buffer
95	Keyboard Self Test
EB	Calling Video BIOS
58	Resetting USB bus
5A	Resetting PATA/SATA bus and all devices
92	Detecting the presence of the keyboard
90	Resetting keyboard
94	Clearing keyboard input buffer
5A	Resetting PATA/SATA bus and all devices
28	Testing memory
90	Resetting keyboard
94	Clearing keyboard input buffer
E7	Waiting for user input
01	INT 19
00	Ready to boot

Solution ID: CS-025434
Date Created: 21-Jan-2007
Last Modified: 01-Jan-2012